You need a verification plan
Good asks include "build a DV plan", "derive DV objectives", or "plan tests, assertions, and coverage."
This is the main multi-step flow implemented in the repo right now. It is for planning verification work for a block or small IP. It does not generate runnable UVM code.
Good asks include "build a DV plan", "derive DV objectives", or "plan tests, assertions, and coverage."
The flow starts with `top_module`, `rtl_files[]`, and a short `design_intent` brief.
Existing CDC or timing reports can be imported as risks, not as proof of full signoff.
Turn the design brief and visible RTL behavior into stable objective IDs.
Map clocks, resets, interfaces, key state, observability points, and unresolved gaps.
Choose the smallest justified environment and a prioritized test list.
Create conservative SVA candidates that match visible block behavior.
Create objective-linked coverpoints, crosses, and exclusions.
Merge all intermediate artifacts and import optional CDC or timing reports as risk inputs.
The timer counter example says the block is CSR-controlled, can load a count, raises `irq` at terminal count, and clears to an idle state on reset.
The assembled plan keeps tests, assertions, and coverage tied to objective IDs and imports timing risk without inventing CDC issues.
The flow applies evidence grounding, output discipline, objective traceability, UVM component selection, assertion classification, coverage taxonomy, and stimulus prioritization.