Write RTL
Start with Verilog or SystemVerilog source files and a small testbench.
Open digital RTL toolchain
From RTL to waveforms to synthesis, with clear guides and official source links.
This hub focuses on the open-source hardware tools most learners need first: write RTL, compile and simulate, inspect waves, then synthesize. Every guide is a portal summary that points back to the official project docs, repos, and license pages instead of mirroring them.
Last verified: April 4, 2026
Linux, macOS, Windows
Official-source-first
Stage map
One toolchain, five simple stages.
Compile and simulate
Use Verilator or Icarus Verilog to check syntax, build, and run simulation.
Inspect waves
Open VCD, FST, or GHW traces in GTKWave to see what the design did over time.
Synthesize
Use Yosys to translate RTL into a gate-level view or a backend-friendly netlist.
Advanced backend
Move into FPGA or ASIC backend tools such as nextpnr, OpenROAD, OpenLane 2, and OpenSTA.
Best first pages
Start with the core stack before the advanced backend tools.
OSS CAD Suite
One bundle that gives you Yosys, Verilator, and several related tools on Linux, macOS, and Windows.
Verilator
Fast compiled simulation, lint-style checks, and a strong path into waveform-driven debugging.
Icarus Verilog
Lightweight Verilog simulation with a simple CLI and good pairing with GTKWave.
GTKWave
Inspect VCD, FST, and related waveform files after simulation.
Yosys
Read RTL, run synthesis passes, and hand designs to FPGA or ASIC backend flows.
Lab, AI flow, ecosystem
After the core stack, move into the end-to-end lab, the AI-agent stage map, or the wider backend ecosystem.