From RTL to waveforms to synthesis, with clear guides and official source links.

This hub focuses on the open-source hardware tools most learners need first: write RTL, compile and simulate, inspect waves, then synthesize. Every guide is a portal summary that points back to the official project docs, repos, and license pages instead of mirroring them.

Start with OSS CAD Suite See the RTL lab flow

Last verified: April 4, 2026 Linux, macOS, Windows Official-source-first

Stage map

One toolchain, five simple stages.

Write RTL

Start with Verilog or SystemVerilog source files and a small testbench.

Compile and simulate

Use Verilator or Icarus Verilog to check syntax, build, and run simulation.

Inspect waves

Open VCD, FST, or GHW traces in GTKWave to see what the design did over time.

Synthesize

Use Yosys to translate RTL into a gate-level view or a backend-friendly netlist.

Advanced backend

Move into FPGA or ASIC backend tools such as nextpnr, OpenROAD, OpenLane 2, and OpenSTA.

Best first pages

Start with the core stack before the advanced backend tools.

Fastest stack setup

OSS CAD Suite

One bundle that gives you Yosys, Verilator, and several related tools on Linux, macOS, and Windows.

Open guide

Compile and simulate

Verilator

Fast compiled simulation, lint-style checks, and a strong path into waveform-driven debugging.

Open guide

Classic simulator

Icarus Verilog

Lightweight Verilog simulation with a simple CLI and good pairing with GTKWave.

Open guide

Wave viewer

GTKWave

Inspect VCD, FST, and related waveform files after simulation.

Open guide

Open-source synthesis

Yosys

Read RTL, run synthesis passes, and hand designs to FPGA or ASIC backend flows.

Open guide

Deeper routes

Lab, AI flow, ecosystem

After the core stack, move into the end-to-end lab, the AI-agent stage map, or the wider backend ecosystem.

RTL lab AI flow Ecosystem

Support matrix

Which path is simplest on each platform?

Tool	Linux	macOS	Windows
Verilator Compiled simulator and lint-style checker	Native package	OSS CAD or source	Native MSVC/CMake
Icarus Verilog Simple RTL simulator	Native package	Homebrew	MSYS2 package
GTKWave Waveform viewer	Package or Flatpak	Community brew tap	Official download
Yosys Open-source synthesis	OSS CAD or package	OSS CAD	OSS CAD
OSS CAD Suite Bundled multi-tool stack	Native bundle	Native bundle	Native bundle
OpenROAD Advanced ASIC backend	Docker/prebuilt	Docker/prebuilt	WSL or Docker
OpenLane 2 Flow wrapper around open ASIC tools	Nix or Docker	Nix or Docker	Docker

Source and copyright policy

These pages are portal summaries. They paraphrase official docs, keep commands short, and link to the upstream project homepages, repos, install docs, and license pages. They do not mirror upstream manuals or reuse project screenshots.

Verilator guide Icarus guide GTKWave guide Yosys guide OSS CAD Suite guide

What comes next

The future video path is already mapped: code RTL, compile and simulate with Verilator, inspect console output, dump a waveform, then open it in GTKWave.

Open lab page See AI-agent mapping