The key idea is simple: do not ask one agent to "do everything." Split the job into stages with clean artifacts, clear handoffs, and a small number of tools per step.
Inputs: spec, interface notes, examples
Outputs: RTL files and a testbench
Artifacts: `.sv`, `.v`, testbench source
Tool: editor, lint, repo context
Agent responsibility: produce small, reviewable source changes and explain assumptions.
Inputs: language features, desired speed, platform
Outputs: selected sim path
Artifacts: command plan
Tool: Verilator or Icarus Verilog
Agent responsibility: pick the smallest tool that fits the design and explain why.
Inputs: RTL, testbench, compile flags
Outputs: logs, executable, pass/fail result
Artifacts: build logs, `obj_dir/`, simulation binary
Tool: Verilator or Icarus
Agent responsibility: run commands, capture logs, and isolate the smallest failing step.
Inputs: simulation outputs
Outputs: trace files and summarized findings
Artifacts: `.vcd`, `.fst`, text logs
Tool: simulator trace output
Agent responsibility: keep the raw artifacts, then summarize what matters.
Inputs: logs, waveforms, expected behavior
Outputs: likely bug class and next fix
Artifacts: issue notes, patch candidates
Tool: GTKWave plus source inspection
Agent responsibility: connect a failing signal pattern back to the responsible RTL or testbench code.
Inputs: RTL that already simulates
Outputs: netlist or synthesis stats
Artifacts: JSON netlist, logs, area/timing summaries
Tool: Yosys
Agent responsibility: run the chosen script, save outputs, and report what changed compared with the RTL-level intent.
Inputs: synthesized design, target platform
Outputs: route, timing, or bitstream path
Artifacts: P&R outputs, timing reports, bitstreams
Tool: nextpnr/openFPGALoader or OpenROAD/OpenLane/OpenSTA
Agent responsibility: select the backend path based on target hardware, not by default habit.