OpenROAD
OpenROAD is the advanced backend toolchain for physical design and signoff-adjacent flow work.
Once you can code RTL, simulate it, inspect waves, and run synthesis, the next tools depend on whether you are targeting FPGA flows, ASIC backend flows, lint and formatting, or Python-based verification.
OpenROAD is the advanced backend toolchain for physical design and signoff-adjacent flow work.
OpenLane 2 wraps several open ASIC tools into a higher-level flow.
OpenSTA is a gate-level static timing analyzer for timing reports and constraint-driven timing checks.
Open-source VHDL simulation with package-manager installs on Linux, MSYS2 on Windows, and Homebrew on macOS.
Python-based testbench framework installed with `pip`, with Linux, macOS, WSL, and Conda guidance in the official docs.
SystemVerilog formatter, linter, and parser tools. The project provides binary releases for Linux and Windows, plus a Homebrew path on macOS.
Open-source place and route for several FPGA architectures. It is primarily a source-build tool, with Homebrew notes on macOS and MSVC/vcpkg notes on Windows.
Use openFPGALoader after nextpnr and bitstream generation when you need to program real FPGA hardware.