Future video page

Write RTL, simulate with Verilator, then inspect the waveform in GTKWave.

This page ships as a text walkthrough first. Later you can drop a recorded video into the reserved slot and keep the same page as the landing area for the full demo.

Video slot reserved

Later: embed the recorded RTL → Verilator → simulation output → GTKWave walkthrough here.

What this lab shows
  • A tiny counter RTL block
  • A simple testbench with waveform dumping
  • Verilator compile and run steps
  • Console output review
  • GTKWave waveform review
Step by step

One small flow from source files to wave inspection.

01

Write the RTL

module counter ( input logic clk, input logic rst_n, output logic [7:0] count ); always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin count <= '0; end else begin count <= count + 1'b1; end end endmodule
02

Write the testbench

module counter_tb; logic clk = 0; logic rst_n = 0; logic [7:0] count; counter dut ( .clk (clk), .rst_n (rst_n), .count (count) ); always begin #5 clk = ~clk; end initial begin $dumpfile("waves.fst"); $dumpvars(0, counter_tb); #12 rst_n = 1; #80 $finish; end endmodule
03

Compile and run with Verilator

verilator --binary --trace-fst -Wall counter.sv counter_tb.sv ./obj_dir/Vcounter_tb

Success looks like the binary running without a fatal error and leaving a `waves.fst` file behind.

04

Check the console output

Look for reset being released, the run completing, and no unexpected runtime assertions or missing-file errors.

05

Open the waveform

gtkwave waves.fst

Add `clk`, `rst_n`, and `count` to the viewer and confirm the counter starts at zero, then increments after reset deasserts.

06

What the viewer should show

You should see the clock toggle, reset hold the output at zero, and the count signal advance once reset is released.

Common pitfalls
  • If `waves.fst` does not appear, check that tracing was enabled and that the testbench called `$dumpfile` and `$dumpvars`.
  • If the Verilator binary name changes, check the generated file names in `obj_dir/`.
  • If GTKWave opens but the design looks flat, add the signals manually from the tree pane.
Next step

Once this basic loop is comfortable, the next stage is usually synthesis with Yosys or turning the same flow into an AI-agent pipeline.