Write RTL, simulate with Verilator, then inspect the waveform in GTKWave.
This page ships as a text walkthrough first. Later you can drop a recorded video into the reserved slot and keep the same page as the landing area for the full demo.
One small flow from source files to wave inspection.
Write the testbench
Compile and run with Verilator
Success looks like the binary running without a fatal error and leaving a `waves.fst` file behind.
Check the console output
Look for reset being released, the run completing, and no unexpected runtime assertions or missing-file errors.
Open the waveform
Add `clk`, `rst_n`, and `count` to the viewer and confirm the counter starts at zero, then increments after reset deasserts.
What the viewer should show
You should see the clock toggle, reset hold the output at zero, and the count signal advance once reset is released.
- If `waves.fst` does not appear, check that tracing was enabled and that the testbench called `$dumpfile` and `$dumpvars`.
- If the Verilator binary name changes, check the generated file names in `obj_dir/`.
- If GTKWave opens but the design looks flat, add the signals manually from the tree pane.
Once this basic loop is comfortable, the next stage is usually synthesis with Yosys or turning the same flow into an AI-agent pipeline.