Focused AI tasks

Skills are the smallest useful units in the repo.

Each skill does one clear engineering job and returns one structured output. The current repo has RTL review skills and DV planning skills, not generic "do everything" agents.

Overview Start Here Skills Rules Block DV Flow

RTL checks

Use these when you want a fast technical read on RTL.

RTL check

RTL CDC Linter

Looks for unsafe clock domain crossings before formal CDC tools run.

Use it when You want a quick CDC audit for a small multi-clock RTL block.

Output One YAML report with crossings, severity, and suggested fixes.

Example The smoke example reports one high-severity unsynchronized single-bit crossing.

RTL check

RTL Timing Path Analyzer

Estimates combinational depth on register-to-register paths before synthesis.

Use it when You want to ask "what are the likely hard paths?" before STA tools.

Output One ranked YAML path report with difficulty labels and suggestions.

Example The simple smoke example marks one reg-to-reg adder path as hard.

DV foundations

Use these first when a block needs a verification plan.

Planning input

Design Intent To DV Objectives

Turns a short design brief and RTL context into stable DV targets.

Use it when You need clear objectives before choosing tests, assertions, or coverage.

Output A YAML list of objective IDs, priorities, categories, and success conditions.

Example The timer-counter example extracts reset, config, count, and interrupt objectives.

Planning input

RTL Verification Surface Extractor

Maps the visible parts of the block that matter for verification.

Use it when You want clocks, resets, interfaces, behaviors, and unresolved gaps in one place.

Output A YAML summary of interfaces, state, behaviors, observability, and unresolved items.

Example The streaming-buffer example records pass-through latency as unresolved.

DV plan builders

Use these after objectives and verification surface are ready.

DV plan builder

UVM Test Matrix Planner

Picks the smallest UVM environment and test list that can verify the stated objectives.

Use it when You want a block-level bench recommendation, test list, and justified agents.

Example The status-fifo example adds active read and write agents plus must-test overflow and underflow.

DV plan builder

SVA Candidate Planner

Suggests conservative assertion candidates that match visible block behavior.

Use it when You want reset, protocol, state, or error properties without guessing missing timing detail.

Example The command-FSM example produces reset, protocol, and error assertion candidates.

DV plan builder

Functional Coverage Planner

Creates deterministic coverpoints, crosses, and exclusions tied to explicit objectives.

Use it when You want meaningful coverage intent instead of decorative coverage.

Example The missing-intent example avoids invented latency bins and records a clear exclusion.

DV plan builder

DV Plan Assembler

Merges the intermediate planning artifacts into one final structured DV plan.

Use it when You want one final plan instead of separate objective, test, assertion, and coverage files.

Example The timer-counter example imports timing risk and keeps all artifacts tied to objective IDs.

Limits matter

These skills are intentionally narrow. Most of them create reports or plans, not runnable UVM code, signoff results, or full-chip verification architecture.

View upstream skill files See how the flow chains them