Verification planning

Build one block-level DV plan from RTL, design intent, and optional front-end audit context.

This flow is for planning verification work for a block or small IP. It can start from direct design_intent plus RTL, or from a block_rtl_package emitted by block-level-rtl-plan. It does not generate runnable UVM code.

Use it when

You need a verification plan

Good asks include "build a DV plan", "derive DV objectives", or "plan tests, assertions, and coverage."

Main inputs

Intent + RTL

The flow starts with top_module, rtl_files[], and a short design_intent brief.

Optional handoff

Block RTL package

A block_rtl_package from block-level-rtl-plan can contribute requirement traceability, spec context, and audit summary inputs.

Step by step

The flow runs six upstream skills in a fixed order.

01

Derive DV objectives

Turn the design brief and visible RTL behavior into stable objective IDs.

02

Extract verification surface

Map clocks, resets, interfaces, key state, observability points, and unresolved gaps.

03

Plan UVM tests

Choose the smallest justified environment and a prioritized test list.

04

Plan assertions

Create conservative SVA candidates that match visible block behavior.

05

Plan coverage

Create objective-linked coverpoints, crosses, and exclusions.

06

Assemble final plan

Merge all intermediate artifacts and import optional CDC or timing reports only as risks, not as proof of signoff.

Output

One final YAML DV plan

The end result is one structured DV plan with objectives, interfaces, environment notes, tests, assertions, coverage, risks, unresolved items, and summary counts.

design -> objectives -> interfaces -> env -> tests -> assertions -> coverage -> risks -> unresolved
Know the limits
  • It does not generate runnable UVM class code.
  • It does not debug regressions.
  • It does not plan SoC-level verification architecture.
  • It does not claim signoff completeness.
Flow composition

The new recommended front-end path is block-level-rtl-plan into block-dv-plan. The DV flow stays grounded in the provided spec and RTL, while reusing the upstream handoff package as planning context.