You need a verification plan
Good asks include "build a DV plan", "derive DV objectives", or "plan tests, assertions, and coverage."
This flow is for planning verification work for a block or small IP. It can start from direct
design_intent plus RTL, or from a block_rtl_package emitted by
block-level-rtl-plan. It does not generate runnable UVM code.
Good asks include "build a DV plan", "derive DV objectives", or "plan tests, assertions, and coverage."
The flow starts with top_module, rtl_files[], and a short design_intent brief.
A block_rtl_package from block-level-rtl-plan can contribute requirement traceability, spec context, and audit summary inputs.
Turn the design brief and visible RTL behavior into stable objective IDs.
Map clocks, resets, interfaces, key state, observability points, and unresolved gaps.
Choose the smallest justified environment and a prioritized test list.
Create conservative SVA candidates that match visible block behavior.
Create objective-linked coverpoints, crosses, and exclusions.
Merge all intermediate artifacts and import optional CDC or timing reports only as risks, not as proof of signoff.
The new recommended front-end path is block-level-rtl-plan into block-dv-plan. The
DV flow stays grounded in the provided spec and RTL, while reusing the upstream handoff package as planning
context.