Build one traceable block-level RTL package from design intent, PPA, architecture, and audits.

block-level-rtl-plan is the front-end flow that turns a high-level block brief into a Markdown microarchitecture spec, synthesizable SystemVerilog, static audit results, and a downstream DV handoff package.

View flow source Open flow catalog

Overview Start Here Skills Rules Flows Block RTL Flow

Use it when

You need an RTL starting point

Good asks include "turn this architecture into RTL", "write a microarchitecture spec", or "create a front-end closure package for this block."

Main inputs

Brief + top module + PPA

The flow starts with top_module, a short design_brief, and explicit performance, power, and area targets.

Important gate

No invented PPA targets

If power, performance, or area goals are missing, the flow records or asks for them instead of pretending it knows the closure target.

Step by step

The flow runs eight upstream skills in order.

Normalize requirements

Turn the brief into deterministic REQ-NNN records, structured context, and explicit open questions.

Write the microarchitecture spec

Emit one Markdown spec with diagrams only when WaveDrom, Mermaid, or BlockDiag clarifies behavior.

Generate RTL

Draft synthesizable SystemVerilog that traces back to the approved spec and requirement IDs.

Run lint audit

Check for structural HDL issues, reset style problems, and synthesizability concerns before deeper analysis.

Run CDC analysis

Classify risky crossings conservatively and carry blocking issues back into RTL revision when needed.

Run RDC analysis

Check reset-domain crossings separately so reset safety is not hidden inside generic CDC review.

Review timing risk

Estimate structurally hard paths and use them as advisory feedback unless the architecture clearly needs redesign.

Assemble the package

Publish one final YAML handoff with requirements, spec path, RTL manifest, audit summary, unresolved items, and DV handoff metadata.

Output

One front-end RTL package

The final package keeps architecture intent, RTL file manifests, audit summaries, unresolved items, and downstream handoff fields in one structured artifact.

requirements -> ppa_targets -> spec -> rtl -> audit_summary -> downstream_handoff

Handoff

Feeds block-level DV planning

The package is designed to flow into block-dv-plan, which can reuse the spec path, requirement traceability, and front-end audit context.

Open the block DV flow Open upstream FLOW.md

Know the limits

It does not replace synthesis, place-and-route, or signoff.
It does not claim physical timing closure or tapeout readiness.
It is block-level front-end planning, not SoC integration planning.